1. Field of the Invention
The present invention generally relates to a method of producing a semiconductor device, and more specifically to an improved method of producing a semiconductor device in which overpolishing at a chemical mechanical polishing time is prevented to eliminate the influence of peripheries on the object part. The present invention is also related to a semiconductor device produced by such a method.
2. Description of the Background Art
In the following description, an alignment mark of a stepper is used as an example of a photo-related mark. FIG. 14 is a cross-sectional view of a densely aggregated pattern (object part) 9 and a chip periphery part (including a dicing part) 8.
Referring to FIG. 14, an oxide film 2 and a nitride film 3 are successively formed on a silicon substrate 1. By a conventional photolithography and etching technique, an isolation part 6 and a photo-related mark part 4 are formed. Referring to FIG. 15, a high-density plasma oxide film 10 is buried in the isolation part 6 and the photo-related mark part 4. This forms an isolation region. According as the size reduction proceeds, the active region will become smaller due to a bird""s beak by the LOCOS technique, so that such an isolation technique is used.
At this time, referring to FIG. 15, the high-density plasma oxide film 10 is formed on the isolation part 6, the photo-related mark part 4 and the nitride film 3, since the high-density plasma oxide film 10 is deposited while maintaining anisotropy. A step difference corresponding to the height of the high-density plasma oxide film 10 formed on the nitride film 3 is generated on the silicon substrate 1. Also, since the active region is small in the densely aggregated pattern (object part) 9, the high-density plasma oxide film 10 is deposited successively from the isolation part 6, and intersects at a central part of the active region. Therefore, as shown in the drawings, the high-density plasma oxide film 10 has a cross section shape like a mountain in the densely aggregated pattern part 9 to form a ridge. The height of the high-density plasma oxide film 10 formed on the active region will be smaller than the thickness of the high-density plasma oxide film 10 formed on the chip peripheral part 8. For this reason, there will be a step difference between a coarse pattern such as the chip peripheral part (including the dicing part) 8 and the densely aggregated pattern (object part) 9.
FIG. 20 is a plan view of the semiconductor device shown in FIG. 15. Namely, FIG. 15 is a cross-sectional view along the line X1-X2 of FIG. 20.
In order not to leave the aforesaid step difference to the later steps, the surface of the silicon substrate 1 is polished by chemical mechanical polishing technique (hereafter referred to as CMP); however, even if it is directly subjected to CMP, the high-density plasma oxide film 10 will remain or the CMP does not stop at the surface of the nitride film and causes overpolishing, since the step difference is too large.
Therefore, in the conventional technique, a resist film 11 is formed on the isolation part 6, as shown in FIG. 16. Next, referring to FIGS. 16 and 17, the high-density plasma oxide film 10 is removed by etching with the use of the resist film 11 as a mask. Hereafter, such removal of a large high-density plasma oxide film 10 on the active region in advance before CMP polishing, will be referred to as pre-etching.
In order to define the size of the active region where the pre-etching is to be performed, a superposition shift at the time of photolithography for pre-etching and the margin of the variation of the resist dimension will be required, Since the high-density plasma oxide film 10 is deposited obliquely at pattern edges, the oblique portion will be 0.4 to 0.5 xcexcm if the deposited amount is 0.4 to 0.5 xcexcm, thereby requiring a margin of 0.4 to 0.5 xcexcm on one side.
Though it depends on the conforming degree of the pre-etching photolithography to the size reduction, the active region that can be pre-etched must have a pattern with a size larger than 1.0 to 2.0 xcexcm. Therefore, it is not possible to pre-etch a fine pattern having an active region smaller than 1.0 xcexcm, such as a memory device cell. Concerning the photo-related mark part 4, the buried high-density plasma oxide film 10 is etched at the pre-etching time, as shown in FIG. 17. This is due to the following reason. In superposition of a transfer gate (TG) and a later-step layer, if a metal-series material is used in the superposed layer, the precision drops if there is no step difference (if it is directly subjected to CMP, it is planarized to remove the step difference) between the superposed layer and the foundation layer (FL).
Even if the high-density plasma oxide film 10 of the photo-related mark part 4 is not etched at the pre-etching time, a step (photolithography, etching) of removing the high-density plasma oxide film 10 of the photo-related mark part 4 is needed somewhere for superposition with the layer in a later step. Therefore, in a prior art technique, the high-density plasma oxide film 10 of the photo-related mark part 4 is etched at the pre-etching time for step reduction (cost reduction).
FIG. 21 corresponds to a plan view of the device shown in FIG. 17. Namely, FIG. 17 is a cross-sectional view along the line X1-X2 of FIG. 21.
Referring to FIG. 21, the high-density plasma oxide film 10 is removed by etching at the photo-related mark part 4.
Referring to FIG. 18, a surface of the silicon substrate 1 is polished by CMP. This removes the high-density plasma oxide film 10 on the nitride film 3. At this time, in the prior art technique, there is a step difference generated at the photo-related mark part 4, and the polishing pressure 13 of CMP is applied thereon to a greater extent than on the other parts, and also slurries caused by chemical polishing are liable to be deposited at the step difference part.
Therefore, at the step difference of the photo-related mark part 4, chemical polishing also proceeds to a greater extent than at the other parts. Also, since the high-density plasma oxide film 10 to be removed by CMP is absent, the nitride film 3 is directly polished at the CMP time, whereby the nitride film 3 is also liable to be shaven. Therefore, if the CMP polishing is carried out to such an extent as to remove the high-density plasma oxide film 10 which is on the nitride film 3 of the densely aggregated pattern 9, overpolishing 14 occurs at and near the center of the photo-related mark part 4. If excessive overpolishing 14 occurs, the region of the densely aggregated pattern 9 will also be overpolished.
Thereafter, referring to FIG. 19, when the nitride film 3 and the pad oxide film 2 are removed by a conventional technique, substrate shaving 15 occurs at the part shown by A in FIG. 19 or the high-density plasma oxide film 10 at the pattern edge drops down to a position below the surface of the silicon substrate 1.
FIG. 22 is a plan view of the device shown in FIG. 19. Namely, FIG. 19 is a cross-sectional view along the line X1-X2 of FIG. 22.
FIG. 23 is a view illustrating a configuration of the photo-related mark part 4 in a conventional object part chip. If a plurality of such photo-related mark parts 4 are aggregated, the polishing pressure at the CMP time is further concentrated to increase the substrate shaving 15 or dropping that starts at that part. As the photo-related mark, there are a global mark used for superposition of a stepper or the like, an LSA mark and an FIA mark used for fine alignment, a mark used for the inspection of superposition, a vernier for eye inspection of photographs, and others. Even with the same mark, if the layers to be superposed are different, the same mark is needed for the number of the layers.
The substrate shaving causes substrate leakage or deterioration of the reliability of the gate oxide film, and dropping at the pattern edge causes an inverse narrow effect of the transistors and humps in the subthreshold characteristics to deteriorate the transistor characteristics. Also, if the degree of overpolishing is too much, the photo-related mark itself cannot be formed properly, and the detection precision also drops.
A principal object of the present invention is to provide an improved method for producing a semiconductor device in which such overpolishing by CMP is prevented to eliminate the influence of peripheries on the object part.
Another object of the present invention is to provide a semiconductor device produced by such a production method.
A method for producing a semiconductor device according to a first aspect of the present invention is directed to a method for producing a semiconductor device having a shallow trench isolation. First, an oxide film and a nitride film are successively formed on a semiconductor substrate in which an object part and a chip peripheral part including a dicing part are to be formed (first step). The oxide film and nitride film are patterned so that an opening is formed in a portion of the chip peripheral part where a photo-related mark is to be formed and in a portion of the object part where a trench is to be formed (second step). A surface of the semiconductor substrate is etched with the use of the patterned oxide film and nitride film as a mask so as to form the trench and to form a recess in the portion where the photo-related mark is to be formed (third step). A plasma oxide film is formed on the semiconductor substrate so as to fill the recess and the trench (fourth step). A resist film is formed on the plasma oxide film so as to cover the trench part and a portion of a neighborhood of the photo-related mark (fifth step). The plasma oxide film is selectively etched with the use of the resist film as a mask so as to leave an overpolish-preventing support member in the neighborhood of the photo-related mark for providing a support against overpolish at a chemical mechanical polishing time (sixth step). The resist film is removed (seventh step). The surface of the semiconductor substrate is polished by chemical mechanical polishing (eighth step). The nitride film and oxide film are removed (ninth step).
According to a preferable embodiment of the present invention, the etching of the sixth step is performed by selecting a pattern of the resist film so that the overpolish-preventing support member is left as a parallel stripe pattern on the plasma oxide film.
According to a further preferable embodiment of the present invention, the etching of the sixth step is performed by selecting a pattern of the resist film so that the overpolish-preventing support member is left as a dot pattern near the photo-related mark.
A method for producing a semiconductor device according to a second aspect of the present invention is directed to a method for producing a semiconductor device having a shallow trench isolation. First, an oxide film and a nitride film are successively formed on a semiconductor substrate in which an object part and a chip peripheral part including a dicing part are to be formed. The oxide film and nitride film are patterned so that an opening is formed in a portion of the chip peripheral part where a photo-related mark is to be formed and in a portion of the object part where a trench is to be formed. A surface of the semiconductor substrate is etched with the use of the patterned oxide film and nitride film as a mask so as to form the trench and to form a recess in the portion where the photo-related mark is to be formed. A plasma oxide film is formed on the semiconductor substrate so as to fill the recess and the trench. A resist film is formed on the plasma oxide film so as to cover the trench part. The plasma oxide film is etched and removed with the use of the resist film as a mask. The resist film is removed. The surface of the semiconductor substrate is polished by chemical mechanical polishing. The nitride film and oxide film are removed. The second aspect of the present invention is characterized in that the photo-related mark is formed in a dispersed configuration instead of a concentrated configuration.
A semiconductor device according to a third aspect of the present invention is directed to a semiconductor device having a shallow trench isolation. The semiconductor device is produced through the following steps. First, an oxide film and a nitride film are successively formed on a semiconductor substrate in which an object part and a chip peripheral part including a dicing part are to be formed. The oxide film and nitride film are patterned so that an opening is formed in a portion of the chip peripheral part where a photo-related mark is to be formed and in a portion of the object part where a trench is to be formed. A surface of the semiconductor substrate is etched with the use of the patterned oxide film and nitride film as a mask so as to form the trench and to form a recess in the portion where the photo-related mark is to be formed. A plasma oxide film is formed on the semiconductor substrate so as to fill the recess and the trench. A resist film is formed on the plasma oxide film so as to cover the trench part and a portion of a neighborhood of the photo-related mark. The plasma oxide film is etched with the use of the resist film as a mask so as to leave an overpolish-preventing support member in the neighborhood of the photo-related mark for providing a support against overpolish at a chemical mechanical polishing time. The resist film is removed. The surface of the semiconductor substrate is polished by chemical mechanical polishing. The nitride film and oxide film are removed. An element is formed in the object part.
According to a preferable embodiment of the present invention, the etching is performed by selecting a pattern of the resist film so that the overpolish-preventing support member is left as a parallel stripe pattern on the plasma oxide film.
According to a further preferable embodiment of the present invention, the etching is performed by selecting a pattern of the resist film so that the overpolish-preventing support member is left as a dot pattern near the photo-related mark.
A semiconductor device according to a fourth aspect of the present invention is directed to a semiconductor device having a shallow trench isolation. The semiconductor device is produced through the following steps. First, an oxide film and a nitride film are successively formed on a semiconductor substrate in which an object part and a chip peripheral part including a dicing part are to be formed. The oxide film and nitride film are patterned so that an opening is formed in a portion of the chip peripheral part where a photo-related mark is to be formed and in a portion of the object part where a trench is to be formed. A surface of the semiconductor substrate is etched with the use of the patterned oxide film and nitride film as a mask so as to form the trench and to form a recess in the portion where the photo-related mark is to be formed. A plasma oxide film is formed on the semiconductor substrate so as to fill the recess and the trench. A resist film is formed on the plasma oxide film so as to cover the trench part. The plasma oxide film is etched and removed with the use of the resist film as a mask. The resist film is removed. The surface of the semiconductor substrate is polished by chemical mechanical polishing. The nitride film and oxide film are removed. An element is formed in the object part. The semiconductor device according to the fourth aspect of the present invention is characterized in that the photo-related mark is formed in a dispersed configuration instead of a concentrated configuration.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.